Digital systems that have two individual circuits with different clock domains may experience metastability problems when the two individual circuits communicate with each other. Metastability may occur when one of the individual circuits (i.e., a first circuit) activates an internal signal during the sampling clock edge of a clock signal of the other circuit (i.e., a second circuit) at a timing that differs from the setup or hold time of the second circuit clock signal. In such cases, the second circuit will have an undefined value for the sampled signal from the first circuit. This may lead to a malfunction or a fault in the second circuit and affect the behavior of one or more digital systems.
U.S. Pat. No. 5,602,878 discloses a method for asynchronously transferring data from a first synchronous sequential logic circuit that derives its clock source from a first clock to a second synchronous sequential logic circuit that derives its clock source from a second clock, whereby metastability of the second synchronous sequential logic circuit is avoided. The invention comprises a data path and a control path, a data synchronizer coupled to the data path for synchronizing data signals, a control synchronizer coupled to the control path for synchronizing control signals, a register coupled in parallel to the data path for storing valid data output from the data synchronizer, a multiplexer having one input coupled to the data path, another input coupled to the register, a selector input coupled to the control path for selecting between receiving as input synchronized data signals or the contents of the register, and an output for transmitting valid data. If metastability is unlikely, the control signal is de-asserted, causing the multiplexer to select the synchronized data as input. If metastability is likely, the synchronized control signal is asserted, causing the multiplexer to select the register as input. The basic test is whether to accept the new state of the data signal, or wait and use the old state currently maintained in the register, until such time as the likelihood of metastability has passed, as indicated by the synchronized control signal.
In the device disclosed in U.S. Pat. No. 5,602,878, there are two digital circuits, only one of which (i.e., the first circuit) is sending data to the other circuit (i.e., the second circuit). There is no way for the first circuit to receive data from the second circuit. The control signals and the data bus have separate synchronizers, which requires two flip-flops per synchronization and therefore, the synchronization depth must be identical for both of them. There is a requirement for a minimum time window of the control signal in order to function correctly. There is a possibility, that the circuit will have an unsynchronized status, wherein that status old data is used.
U.S. Pat. No. 5,256,912 discloses a synchronizer that utilizes a plurality of clocking signals generated by a specialized clocking circuit, in conjunction with synchronizer modules incorporating transparent latches, to synchronize signals passing from a first clock domain to a second clock domain. Two types of synchronizer modules are disclosed, a single synchronizer module and a multiple synchronizer module. Both types of synchronizer modules utilize a “basic synchronizer cell” comprised of two transparent latches in series. The single synchronizer module is comprised of two such basic synchronizer cells, and utilizes a plurality of clocking signals that are coupled to the transparent latches to accomplish synchronization. The multiple synchronizer module also utilizes a plurality of clocking signals, and is comprised of a plurality of single synchronizer modules coupled in parallel and a synchronizer selector circuit. The multiple synchronizer module operates by initially coupling the signal to be synchronized to the synchronizer selector circuit, which then sequentially couples the signal to successive single synchronizer modules.
The device disclosed in U.S. Pat. No. 5,256,912 enables each of the circuits to transfer data to the other circuit by using the same basic cell, but there is no way for one circuit to request and receive data from the other circuit. In order to synchronize between the two circuits, there is a need to generate a series of four new clocks.
U.S. Pat. No. 5,291,529 discloses a method for improving the performance of the transferring of transaction handshakes between sections of synchronous logic which are in different timing domains, providing immunity from set-up and hold violations and associated problems of metastability, by reducing the time overhead required for signal synchronization.
U.S. Pat. No. 5,132,990 discloses a synchronizer that samples and stores the synchronized data with a transparent latch instead of a flip-flop or similar device to avoid the long set-up time required by such devices. The synchronizer compares its input level to its output level. When they are found to be different because of an input data change, the difference is used to gate the system clock, which in turn gates the transparent latch to sample and store the changed input data level as the new data output level. Since the change in the input data gates the system clock, which further gates the opening of the latch, the input data is essentially guaranteed to fulfill the latch set-up time requirements. For the difficult case in which the input data change occurs as the clock is changing states, a Schmidt trigger is inserted ahead of the latch gating input. The Schmidt trigger will both respond and provide a proper pulse width and magnitude to drive the latch without metastability, or it will pass a “runt pulse” and not respond to it. The latch gating input likewise will not respond to the “runt pulse” because of the pulse's insufficient duration or level. Thus, the Schmidt trigger acts as a matched filter to prevent metastability problems from any runt pulses. All the methods described above have not yet provided satisfactory solutions to the problem of metastability that occurs during two-way communications between circuits having different clock domains.
It would therefore be desirable to have an apparatus and method that is capable of transferring data in a write/read operation between individual circuits that have different clock domains without experiencing metastability problems during the data transfer.